AS7C256A-20JC - Alliance Semiconductor

Alliance AS7C256A-20JC SRAM 5V 32K X 8 CMOS SRAM Features AS7C256A (5V version) Industrial and commercial temperature Organization: 32,768 words × 8 bits High speed - 10/12/15/20 ns address access time - 3/3/4/5 ns output enable access time Very low power consumption: ACTIVE - 495mW (AS7C256A) / max @ 10 ns Very low power consumption: STANDBY - 11 mW (AS7C256A) / max CMOS I/O - 3.6 mW (AS7C3256A) / max CMOS I/O Latest 6T 0.25u CMOS technology 2.0V data retention Easy memory expansion with CE and OE inputs TTL-compatible, three-state I/O 28-pin JE3256A) / max @ 10 nsDEC standard packages - 300 mil SOJ - 8 × 13.4 TSOP ESD protection ≥ 2000 volts Latch-up current ≥ 200 mA Functional description The AS7C(3)256A is a 5V/3.3V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized as 32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage, including PentiumTM, PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques permit 3.3V operation without sacrificing performance or operating margins. The device enters standby mode when CE is high. CMOS standby mode consumes ≤3.6 mW. Normal operation offers 75% power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode. Both versions of the AS7C256A offer 2.0V data retention. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 3/3/4/5 ns are ideal for high-performance applications. The chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations. A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/ O pins